This invention relates to general purpose data processors, and in particular, to such data processors having a writable instruction set with a hardware stack.
Since the advent of computers, attempts have been made to make computers smaller, with increased memory and with faster operation. Recently, minicomputers and microcomputers have been built which have the memory capacity of original mainframe computers. Most of these computers are referred to as "complex instruction set" computers. Because of the use of complex instruction sets, these computers tend to be relatively slow in operation as compared to computers designed for specific applications. However, they are able to perform a wide variety of programs because of their ability to process instruction sets corresponding to the source programs run on them.
More recently, "reduced instruction set" computers have been developed which can execute programs more quickly than the complex instruction set computers. However, these computers tend to be limited in that the instruction sets are reduced to only those instructions which are used most often. Infrequently used instructions are eliminated to reduce hardware complexity and to increase hardware speed. Such computers provided limited semantic efficiency in applications for which they were not designed. The large semantic gaps cannot be tilled easily. Emulation of complex but frequently used instructions is always a less efficient solution and significantly reduces the initial speed advantage. Thus, such computers provide limited general applicability.
The present invention provides a computer having general purpose applicability by increasing flexibility while providing substantially improved speed of operation by minimizing complexity, as compared to conventional computers. The invention provides this in a way which uses simple, inexpensive, and commonly available components. Further, the invention minimizes hardware and software tool costs.
More specifically, the present invention provides a computer having a main program memory, a writable microprogram memory, an arithmetic logic unit, and a stack memory all connected to a single common data bus. In a preferred embodiment, this invention provides a computer interface for use with a host computer. Further, more specifically, both a data stack and a subroutine return stack are provided, each associated with a pointer which may be set to any element in the corresponding stack without affecting the contents of the stack. Further, there is a direct communication link between the main program memory and the microprogram memory which is separate from the data bus. This provides overlapped instruction fetching and execution. The data high input to the ALU can be used as a register serving as the top of the stack but it is not necessary. By user determined convention the DHI register is designated as the top of the stack. Other computer architectures must designate a register as the top of the stack and usually dedicate a register as such.
Additionally, an instruction set is preferably coded using a plurality of bits in a selected pattern for denoting a microcoded primltive, as opposed to a procedure call in order to increase the amount of addressable memory. The use of an operations code value as a page address into microprogram memory serves a double function allowing the computer to run more efficiently. A writable microprogram memory allows the computer to be run using various lanquages and for different applications. An identical parameter passing mechanism is used for both subroutines and microcoded primitives. This means that a subroutine can be transparently replaced with a microcoded primitive with no impact on other software.
The unique combination of simple hardware linked with hardware stacks leads to a general purpose computer design with an increased efficiency of instruction execution. The user microprogramability of a writable instruction set optimized to application requirements leads to increased semantic content for the instruction set. The combination of these two features leads to increased processor throughput at any specified clock speed when compared to that possible with conventional complex instruction set computers (CISC) and reduced instruction set computers (RISC).
It will be seen that such a computer offers substantial optimization of throughput while maintaining flexibility. These and other advantages and features of the invention will be more clearly understood from a consideration of the drawings and the following detailed description of the preferred embodiment.